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May 2005 Preliminary
(R)
AS7C4096A
5.0V 512K x 8 CMOS SRAM Features
* Pin compatible to AS7C4096 * Industrial and commercial temperature * Organization: 524,288 words x 8 bits * Center power and ground pins * High speed
- 10/12/15/20 ns address access time - 5/6 ns output enable access time
* Equal access and cycle times * Easy memory expansion with CE, OE inputs * TTL-compatible, three-state I/O * JEDEC standard packages * ESD protection 2000 volts * Latch-up current 200 mA
- 400 mil 36-pin SOJ - 44-pin TSOP 2
* Low power consumption: ACTIVE
- 880mW/max @ 10 ns
* Low power consumption: STANDBY
- 55mW/max CMOS
Logic block diagram
VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 I/O1
Pin arrangements
36-pin SOJ (400 mil)
A0 A1 A2 A3 A4 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O8 I/O7 GND VCC I/O6 I/O5 A14 A13 A12 A11 A10 NC NC NC A0 A1 A2 A3 A4 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A5 A6 A7 A8 A9 NC NC
44-pin TSOP 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE I/O8 I/O7 GND VCC I/O6 I/O5 A14 A13 A12 A11 A10 NC NC NC
Row decoder
524,288 x 8 Array (4,194,304)
Sense amp
I/O8 Column decoder A10 A11 A12 A13 A14 A15 A16 A17 A18 WE OE CE
Control Circuit
Selection guide
Maximum address access time Maximum outputenable access time Maximum operating current Maximum CMOS standby current -10 10 5 160 10 -12 12 6 140 10 -15 15 6 120 10 -20 20 6 100 10 Unit ns ns mA mA
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AS7C4096A
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Functional description
The AS7C4096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1-I/O8 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5.0V supply voltage. This device is available as per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
Absolute maximum ratings
Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Temperature with VCC applied DC current into output (low) Symbol Vt1 Vt2 PD Tstg Tbias IOUT Min -0.5 -0.5 - -65 -55 - Max +7.0 VCC +0.5 1.0 +150 +125 20 Unit V V W C C mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE WE OE Data Mode
H L L L
X H H L
X H L X
High Z High Z DOUT DIN
Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC)
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Recommended operating condition
Parameter Supply voltage Input voltage Ambient operating temperature
*
commercial industrial
Symbol VCC(10/12/15/20) VIH* VIL** TA TA
Min 4.5 2.2 -0.5 0 -40
Nominal 5.0 - - - -
Max 5.5 VCC + 0.5 0.8 70 85
Unit V V V C C
VIH max = VCC + 1.5V for pulse width less than 5 nS. ** VIL min = -1.0V for pulse width less than 5 nS.
.
DC operating characteristics (over the operating range)1
Parameter Input leakage current Output leakage current Operating power supply current Symbol |ILI| |ILO| ICC ISB Standby power supply current Test conditions VCC = Max, VIN = GND to VCC VCC = Max, CE = VIH VOUT= GND to VCC VCC = Max, CE < VIL f = fMax, IOUT = 0mA VCC = Max, CE > VIH f = fMax, IOUT = 0mA VCC = Max, CE VCC - 0.2V, VIN 0.2V or VIN VCC - 0.2V, f=0 IOL = 6 mA, VCC = Min IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min -10 -12 -15 -20 Min Max Min Max Min Max Min Max Unit Notes - - - - 1 1 160 60 - - - - 1 1 140 55 - - - - 1 1 120 50 - - - - 1 1 100 40 A A mA mA
ISB1
- - - 2.4
10 0.4 0.5 -
- - - 2.4
10 0.4 0.5 -
- - - 2.4
10 0.4 0.5 -
- - - 2.4
10 0.4 0.5 -
mA
Output voltage
VOL VOH
V V
4 4
Capacitance (f = 1MHz, Ta = 25 C, VCC = NOMINAL)4
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF
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Read cycle (over the operating range)2,8
Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE Low to output in low Z CE High to output in high Z OE Low to output in low Z OE High to output in high Z Power up time Power down time Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tOHZ tPU tPD Min 10 - - - 3 3 - 0 - 0 - -10 Max - 10 10 5 - - 5 - 5 - 10 Min 12 - - - 3 3 - 0 - 0 - -12 Max - 12 12 6 - - 6 - 6 - 12 Min 15 - - - 3 3 - 0 - 0 - -15 Max - 15 15 6 - - 7 - 7 - 15 Min 20 - - - 3 3 - 0 - 0 - -20 Max - 20 20 6 - - 9 - 9 - 20 Unit Notes ns ns ns ns ns ns ns ns ns ns ns 4 3,4 3,4 3,4 3,4 3,4 3,4 2 2
Key to switching waveforms
Rising input Falling input Undefined/don't care
Read waveform 1 (address controlled)2,5,6,8
tRC Address tAA DOUT Data valid tOH
Read waveform 2 (CE, OE controlled)2,5,7,8
tRC1 CE tOE OE tOLZ tACE DOUT tCLZ Supply current tPU 50% Data valid tPD 50% ICC ISB tOHZ tCHZ
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Write cycle (over the operating range)9
Parameter Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width (OE = high) Write pulse width (OE = low Address hold from end of write Write recovery time Data valid to write end Data hold time Write enable to output in high Z Output active from write end -10 Symbol Min Max tWC tCW tAW tAS tWP1 tWP2 tAH tWR tDW tDH tWZ tOW 10 7 7 0 7 10 0 0 5 0 2 3 - - - - - - - - - - 5 - -12 Min Max 12 8 8 0 8 12 0 0 6 0 2 3 - - - - - - - - - - 6 - -15 Min Max 15 10 10 0 10 15 0 0 7 0 2 3 - - - - - - - - - - 7 - -20 Min Max 20 12 12 0 12 20 0 0 9 0 2 3 - - - - - - - - - - 9 - Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns 3,4 3,4 3,4
Write waveform 1 (WE controlled)9
tWC tAW Address WE tAS DIN tWZ DOUT tWP tDW Data valid tOW tDH tWR tAH
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Write waveform 2 (CE controlled)9
tWC tAW Address tAS CE WE DIN tWP tDW Data valid tDH tCW tWR tAH
AC test conditions
Output load: see Figure B. Input pulse level: GND to VCC - 0.5V. See Figures A and B. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V.
DOUT 255
+5.0V 480 C10
Thevenin equivalent: 168 DOUT +1.728V
VCC - 0.5V
GND
90% 10%
90% 10%
2 ns Figure A: Input pulse
GND Figure B: 5.0V Output load
Notes
1 2 3 4 5 6 7 8 9 10 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. For test conditions, see AC Test Conditions. tCLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is HIGH for read cycle. CE and OE are LOW for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. All write cycle timings are referenced from the last valid address to the first transitioning address. C = 30pF, except at high Z and low Z parameters, where C = 5pF.
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Package dimensions
44434241403938 37 36 35 34333231 30 29 28 2726 2524 23
c
44-pin TSOP 2
E1 E
1 2 3 4 5 6 7 8 9 10 111213 14 15 16 17 1819 20 21 22
d
A A1 b e A2 L 0-5
A A1 A2 b c d E1 E e L
44-pin TSOP 2 Min(mm) Max(mm) 1.2 0.05 0.15 0.95 1.05 0.30 0.45 0.21 0.12 18.31 18.52 10.06 10.26 11.68 11.94 0.80 (typical) 0.40 0.60 36-pin SOJ 400 Min(mils) Max(mils) 0.128 0.148 0.025 - 0.105 0.115 0.015 0.020 0.026 0.032 0.007 0.013 .920 .930 0.045 0.055 0.370 BSC 0.395 0.405 0.435 0.445
e
D b1 36-pin SOJ E1 E2 A1 b c A2 E Seating Plane A
Pin 1
A A1 A2 b b1 c D e E E1 E2
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Ordering codes
Package SOJ TSOP 2 Version Commercial Industrial Commercial Industrial 10 ns AS7C4096A-10JC AS7C4096A-10JI AS7C4096A-10TC AS7C4096A-10TI 12 ns AS7C4096A-12JC AS7C4096A-12JI AS7C4096A-12TC AS7C4096A-12TI 15 ns AS7C4096A-15JC AS7C4096A-15JI AS7C4096A-15TC AS7C4096A-15TI 20 ns AS7C4096A-20JC AS7C4096A-20JI AS7C4096A-20TC AS7C4096A-20TI
Note: Add suffix `N' to the above part number for Lead Free Parts. (Ex: AS7C4096A - 10 TIN)
Part numbering system
AS7C SRAM prefix 4096A Device number -XX Access time J or T Packages: J: SOJ 400 mil T: TSOP 2 X Temperature ranges: C: Commercial, 0C to 70C I: Industrial, -40C to 85C X N=Lead Free Parts
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Revision History
Rev. No. v1.0 v1.1 Initial release Included ICC, ISB & ISB1 parameters Corrected the following: TOE, VIH, VOL & tWZ History Revised Date 11/08/04 05/27/05
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Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com
Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: AS7C4096A Document Version: v. 1.1
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such lifesupporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

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